Key Responsibilities:
- Lead the development of digital instruments (e.g., scan engines, vector cards, high-speed I/O cards) for SoC, memory, MCU, CPU, GPU, and FPGA test applications.
- Design and validate digital interface boards for PXI-based systems or custom ATE/STS racks, including timing, control logic, and signal integrity.
- Design instrumentation capable of supporting high-speed interface protocols, such as PCIe, MIPI, Ethernet, USB, Thunderbolt, etc.
- Collaborate with system and FPGA teams to ensure timing alignment, protocol compliance, and signal integrity.
- Implement and support digital testing protocols including JTAG, Boundary Scan, MBIST, LBIST, and functional scan.
- Translate vector-level test requirements into hardware and firmware solutions (e.g., Vector Depth, I/O Format, Rep-rate, Scan Vector, Edge timing).
- Benchmark and reverse-engineer commercial ATE platforms (e.g., Teradyne, Advantest, NI STS, Chroma) to enhance internal test platform features.
- Provide technical mentorship, support hiring, and manage a small engineering team.
- Participate in product roadmap discussions, customer engagements, and internal architecture reviews.
Required Qualifications:
- Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field.
- Minimum 8 years experience in ATE hardware development, SoC testing, or digital test instrumentation.
- Experience designing instrument or interface boards, especially for PXI-based or custom ATE/STS systems.
- Solid understanding of vector handling and digital test architectures (e.g., vector engine, pattern generation, timing).
- Exposure to high-speed digital interfaces (e.g., PCIe, MIPI, USB, Ethernet) in either instrumentation design or test validation.
- Familiar with signal integrity, jitter margining, and timing closure at the board level.
- Comfortable with scripting or automation tools (e.g., Python, TCL, LabVIEW or equivalent).
- Strong team and project coordination skills with technical mentoring experience.